1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device that uses a data strobe signal.
2. Description of Related Art
The frequency of data transfer between a plurality of semiconductor devices, for example, between a semiconductor memory device and a memory controller, has been increasing year by year. Thus, in order to show data loading timing, improvement of accuracy of a data strobe signal has been more and more important; the data strobe signal is fed from a data-outputting semiconductor device (for example, the semiconductor memory device) to a data-receiving semiconductor device (for example, the memory controller) together with data.
JP2008-112565A discloses a semiconductor device that uses as a data strobe signal two data strobe signals with different phases (these signals are hereinafter referred to as complementary data strobe signals). According to JP2008-112565A, even if the time required for the rising edge of the complementary data strobe signals is different from that required for the falling edge of the complementary data strobe signals, the period of the complementary data strobe signals (the time between cross points of the complementary data strobe signals) can be kept constant.
In general, such a semiconductor device as described in JP2008-112565A is designed such that the potentials of the cross points of the complementary data strobe signals are equal to the intermediate potential (for example, intermediate potential Vtt) of the maximum amplitude of the data strobe signals (for example, the amplitude between power supply potential VDD and ground potential VSS). This design is intended to allow the timing when the complementary data strobe signals cross each other to coincide with the timing when the logical level of the data signal is switched. The data-receiving semiconductor device can receive accurate data signals during a predetermined period by making the potentials of the cross points of the complementary data strobe signals equal to the intermediate potential Vtt.
However, in the actual semiconductor device, the potentials of the cross points of the complementary data strobe signals may deviate from the intermediate potential Vtt. The present inventor has clarified that in this case, the timing when the complementary data strobe signals cross each other may disadvantageously deviate from the timing when the logical level of the data signal is switched.
The deviation between the period of the complementary data strobe signals and the period of the data signal may disadvantageously lead to a reduced period available for data loading or to loading of erroneous data.
A possible method for adjusting the potentials of the cross points of the complementary data strobe signals is to adjust the drive capability of an output circuit for the data strobe signals and thus the slew rate of the complementary data strobe signals. However, a change in the slew rate of the complementary data strobe signals may degrade signal quality such as the result of a change in signal reflection.